sas2026/tinyriscv
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basic instruction format

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inixyz
2023-10-07 02:36:16 +03:00
parent 55cf6929c3
commit 395b67f0e5
1 changed files with 42 additions and 0 deletions
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42
src/main.c
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@@ -18,6 +18,28 @@ static inline uint32_t select_bits(const uint32_t val, const uint8_t end,
return val >> start & (1 << len - 1); return val >> start & (1 << len - 1);
} }
void add(tinyrv_cpu* cpu, ){
reg_file[rd] = reg_file[rs1] + reg_file[rs2];
}
void R_type(){
switch(func3){
case 0x0: // ADD/SUB
if(func7 == 0x00) reg_file[rd] = reg_file[rs1] + reg_file[rs2];
else if(func7 == 0x20) reg_file[rd] = reg_file[rs1] - reg_file[rs2];
break;
case /*SLL*/ 0x1: regs[rd] = regs[rs1] << (regs[rs2] & 0b11111); break;
case /*SLT*/ 0x2: regs[rd] = (int32_t)regs[rs1] < (int32_t)regs[rs2]; break;
case /*SLTU*/ 0x3: regs[rd] = regs[rs1] < regs[rs2]; break;
case /*XOR*/ 0x4: regs[rd] = regs[rs1] ^ regs[rs2]; break;
}
}
void tinyrv_step(tinyrv_cpu* cpu){ void tinyrv_step(tinyrv_cpu* cpu){
//instruction fetch //instruction fetch
const uint32_t inst = load32(cpu->memory, cpu->pc); const uint32_t inst = load32(cpu->memory, cpu->pc);
@@ -29,6 +51,26 @@ void tinyrv_step(tinyrv_cpu* cpu){
#define rs2 select_bits(inst, 24, 20) #define rs2 select_bits(inst, 24, 20)
const uint8_t opcode = select_bits(inst, 6, 0); const uint8_t opcode = select_bits(inst, 6, 0);
switch(func3){
}
switch(opcode){
case LUI:
case R_type:{
switch(func3){
case addsub:
switch(func7){
}
}
}
}
} }
int main(){ int main(){