This commit is contained in:
inixyz
2023-10-08 17:19:56 +03:00
parent b9ab9c301d
commit 06ed17b51a

87
main.c
View File

@@ -7,46 +7,18 @@ typedef struct{
const uint32_t MEM_OFFSET = 0x80000000; const uint32_t MEM_OFFSET = 0x80000000;
static inline uint8_t load8(const uint8_t* memory, const uint32_t addr){ static inline uint8_t load8(const uint8_t* mem, const uint32_t addr){
return memory[addr - MEM_OFFSET]; return mem[addr - MEM_OFFSET];
} }
static inline uint16_t load16(const uint8_t* memory, const uint32_t addr){ static inline uint16_t load16(const uint8_t* mem, const uint32_t addr){
return *(uint16_t*)(memory + addr - MEM_OFFSET); return *(uint16_t*)(mem + addr - MEM_OFFSET);
} }
static inline uint32_t load32(const uint8_t* memory, const uint32_t addr){ static inline uint32_t load32(const uint8_t* mem, const uint32_t addr){
return *(uint32_t*)(memory + addr - MEM_OFFSET); return *(uint32_t*)(mem + addr - MEM_OFFSET);
} }
static inline uint8_t decode_opcode(const uint32_t inst){
return inst & 0x7f;
}
static inline uint8_t decode_func3(const uint32_t inst){
return inst >> 12 & 0x7;
}
static inline uint8_t decode_func7(const uint32_t inst){
return inst >> 25 & 0x7f;
}
static inline uint8_t decode_rd(const uint32_t inst){
return inst >> 7 & 0x1f;
}
static inline uint8_t decode_rs1(const uint32_t inst){
return inst >> 15 & 0x1f;
}
static inline uint8_t decode_rs2(const uint32_t inst){
return inst >> 20 & 0x1f;
}
// static inline int16_t decode_imm_I(const uint32_t inst){
// }
void R_type(const uint8_t func3, const uint8_t func7, uint32_t regs[32], void R_type(const uint8_t func3, const uint8_t func7, uint32_t regs[32],
const uint8_t rd, const uint8_t rs1, const uint8_t rs2){ const uint8_t rd, const uint8_t rs1, const uint8_t rs2){
@@ -63,7 +35,9 @@ void R_type(const uint8_t func3, const uint8_t func7, uint32_t regs[32],
case /*SRL/SRA*/ 0x5: case /*SRL/SRA*/ 0x5:
if(func7 == /*SRL*/ 0x00) regs[rd] = regs[rs1] >> (regs[rs2] & 0x1f); if(func7 == /*SRL*/ 0x00) regs[rd] = regs[rs1] >> (regs[rs2] & 0x1f);
else if(func7 == /*SRA*/ 0x20) regs[rd] = (int32_t)regs[rs1] >> (regs[rs2] & 0x1f); else if(func7 == /*SRA*/ 0x20){
regs[rd] = (int32_t)regs[rs1] >> (regs[rs2] & 0x1f);
}
break; break;
case /*OR*/ 0x6: regs[rd] = regs[rs1] | regs[rs2]; break; case /*OR*/ 0x6: regs[rd] = regs[rs1] | regs[rs2]; break;
@@ -71,29 +45,44 @@ void R_type(const uint8_t func3, const uint8_t func7, uint32_t regs[32],
} }
} }
// void L_type(){ void L_type(const uint8_t func3, uint32_t regs[32], const uint8_t rd,
const uint8_t* mem, const uint8_t rs1, const int16_t imm){
// switch(func3){ switch(func3){
// case /*LB*/ 0x0: regs[rd] = (int32_t)(int8_t)load8(mem, regs[rs1] + ) break; case /*LB*/ 0x0:
// } regs[rd] = (int32_t)(int8_t)load8(mem, regs[rs1] + (int32_t)imm);
// } break;
case /*LH*/ 0x1:
regs[rd] = (int32_t)(int16_t)load16(mem, regs[rs1] + (int32_t)imm);
break;
case /*LW*/ 0x2: regs[rd] = load32(mem, regs[rs1] + (int32_t)imm); break;
case /*LBU*/ 0x4: load8(mem, regs[rs1] + (int32_t)imm); break;
case /*LHU*/ 0x5: load16(mem, regs[rs1] + (int32_t)imm); break;
}
}
void step(Cpu* cpu){ void step(Cpu* cpu){
//instruction fetch //fetch
const uint32_t inst = load32(cpu->mem, cpu->pc); const uint32_t inst = load32(cpu->mem, cpu->pc);
cpu->pc += 4; cpu->pc += 4;
//instruction decoding //decode
#define opcode decode_opcode(inst) #define opcode (inst & 0x7f)
#define func3 decode_func3(inst) #define func3 (inst >> 12 & 0x7)
#define func7 decode_func7(inst) #define func7 (inst >> 25 & 0x7f)
#define rd decode_rd(inst) #define rd (inst >> 7 & 0x1f)
#define rs1 decode_rs1(inst) #define rs1 (inst >> 15 & 0x1f)
#define rs2 decode_rs2(inst) #define rs2 (inst >> 20 & 0x1f)
#define imm_I ((int32_t)inst >> 20)
//execute //execute
cpu->regs[0] = 0;
switch(opcode){ switch(opcode){
case /*R-type*/ 0x33: R_type(func3, func7, cpu->regs, rd, rs1, rs2); break; case 0x03: L_type(func3, cpu->regs, rd, cpu->mem, rs1, imm_I); break;
case 0x33: R_type(func3, func7, cpu->regs, rd, rs1, rs2); break;
} }
} }