sas2026/tinyriscv
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refactor and R-type instructions

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This commit is contained in:
inixyz
2023-10-07 22:33:08 +03:00
parent 395b67f0e5
commit 02aaf2db57
3 changed files with 31 additions and 41 deletions
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2
.gitignore vendored
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@@ -1 +1 @@
tinyrv tinyriscv

2
makefile
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@@ -1,2 +1,2 @@
default: default:
gcc src/*.c -o tinyrv gcc src/main.c -o tinyriscv

68
src/main.c
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@@ -1,9 +1,9 @@
#include <stdint.h> #include <stdint.h>
typedef struct{ typedef struct{
uint32_t registers[32], pc; uint32_t regs[32], pc;
uint8_t* memory; uint8_t* mem;
}tinyrv_cpu; }Cpu;
const uint32_t MEMORY_OFFSET = 0x80000000; const uint32_t MEMORY_OFFSET = 0x80000000;
@@ -18,62 +18,52 @@ static inline uint32_t select_bits(const uint32_t val, const uint8_t end,
return val >> start & (1 << len - 1); return val >> start & (1 << len - 1);
} }
void add(tinyrv_cpu* cpu, ){ void R_type(const uint8_t func3, const uint8_t func7, uint32_t regs[32],
const uint8_t rd, const uint8_t rs1, const uint8_t rs2){
reg_file[rd] = reg_file[rs1] + reg_file[rs2];
}
void R_type(){
switch(func3){ switch(func3){
case 0x0: // ADD/SUB case /*ADD/SUB*/ 0x0:
if(func7 == 0x00) reg_file[rd] = reg_file[rs1] + reg_file[rs2]; if(func7 == /*ADD*/ 0x00) regs[rd] = regs[rs1] + regs[rs2];
else if(func7 == 0x20) reg_file[rd] = reg_file[rs1] - reg_file[rs2]; else if(func7 == /*SUB*/ 0x20) regs[rd] = regs[rs1] - regs[rs2];
break; break;
case /*SLL*/ 0x1: regs[rd] = regs[rs1] << (regs[rs2] & 0b11111); break; case /*SLL*/ 0x1: regs[rd] = regs[rs1] << (regs[rs2] & 0x1f); break;
case /*SLT*/ 0x2: regs[rd] = (int32_t)regs[rs1] < (int32_t)regs[rs2]; break; case /*SLT*/ 0x2: regs[rd] = (int32_t)regs[rs1] < (int32_t)regs[rs2]; break;
case /*SLTU*/ 0x3: regs[rd] = regs[rs1] < regs[rs2]; break; case /*SLTU*/ 0x3: regs[rd] = regs[rs1] < regs[rs2]; break;
case /*XOR*/ 0x4: regs[rd] = regs[rs1] ^ regs[rs2]; break; case /*XOR*/ 0x4: regs[rd] = regs[rs1] ^ regs[rs2]; break;
case /*SRL/SRA*/ 0x5:
if(func7 == /*SRL*/ 0x00) regs[rd] = regs[rs1] >> (regs[rs2] & 0x1f);
else if(func7 == /*SRA*/ 0x20) regs[rd] = (int32_t)regs[rs1] >> (regs[rs2] & 0x1f);
break;
case /*OR*/ 0x6: regs[rd] = regs[rs1] | regs[rs2]; break;
case /*AND*/ 0x7: regs[rd] = regs[rs1] & regs[rs2]; break;
}
} }
} void step(Cpu* cpu){
void tinyrv_step(tinyrv_cpu* cpu){
//instruction fetch //instruction fetch
const uint32_t inst = load32(cpu->memory, cpu->pc); const uint32_t inst = load32(cpu->mem, cpu->pc);
cpu->pc += 4; cpu->pc += 4;
//instruction decoding //instruction decoding
#define opcode select_bits(inst, 6, 0)
#define func3 select_bits(inst, 14, 12)
#define func7 select_bits(inst, 31, 25)
#define rd select_bits(inst, 11, 7) #define rd select_bits(inst, 11, 7)
#define rs1 select_bits(inst, 19, 15) #define rs1 select_bits(inst, 19, 15)
#define rs2 select_bits(inst, 24, 20) #define rs2 select_bits(inst, 24, 20)
const uint8_t opcode = select_bits(inst, 6, 0); //execute
switch(func3){
}
switch(opcode){ switch(opcode){
case LUI: case /*R-type*/ 0x33: R_type(func3, func7, cpu->regs, rd, rs1, rs2); break;
//case /*I-type*/ 0x03: I_type(); break;
//case /*S-type*/ 0x23: S_type(); break;
//case /*B-type*/ 0x63: B_type(); break;
case R_type:{
switch(func3){
case addsub:
switch(func7){
}
}
}
} }
} }
int main(){ int main(){
tinyrv_cpu cpu;
cpu.pc = MEMORY_OFFSET;
} }